1. Field of the Invention
The present invention generally relates to data processing techniques and, in particular, to a system and method for dynamically reallocating memory in a computer system while ensuring that the reallocation does not introduce data errors.
2. Related Art
Large computer systems (or servers) often employ a plurality of memory units to provide enough instruction and data memory for various applications. Each memory unit has a large number of memory locations of one or more bits where data can be stored, and each memory location is associated with and identified by a particular memory address, referred to hereafter as xe2x80x9cmemory unit address.xe2x80x9d When an instruction that stores data is executed, a bus address defined by the instruction is used to obtain a memory unit address, which identifies the memory location where the data is actually to be stored. In this regard, a mapper is often employed that maps or translates the bus address into a memory unit address having a different value than the bus address. There are various advantages associated with utilizing bus addresses that are mapped into different memory unit addresses.
For example, many computer applications are programmed such that the bus addresses are used consecutively. In other words, one of the bus addresses is selected as the bus address to be first used to store data. When a new bus address is to be utilized for the storage of data, the new bus address is obtained by incrementing the previously used bus address.
If consecutive bus addresses are mapped to memory unit addresses in the same memory unit, then inefficiencies may occur. In this regard, a finite amount of time is required to store and retrieve data from a memory unit. If two consecutive data stores occur to the same memory unit, then the second data store may have to wait until the first data store is complete before the second data store may occur. However, if the two consecutive data stores occur in different memory units, then the second data store may commence before the first data store is complete. To minimize memory latency and maximize memory bandwidth, consecutive bus addresses should access as many memory units as possible. This can also be described as maximizing the memory interleave.
As a result, the aforementioned mapper is often designed to map the bus addresses to the memory unit addresses such that each consecutive bus address is translated into a memory unit address in a different memory unit. For example, a bus address having a first value is mapped to a memory unit address identifying a location in a first memory unit, and the bus address having the next highest value is mapped to a memory unit address identifying a location in a second memory unit. Therefore, it is likely that two consecutive data stores from a single computer application do not occur in the same memory unit. In other words, it is likely that consecutive data stores from a computer application are interleaved across the memory units.
There are situations when it is desirable to move the data values stored in some locations of one or more of the memory units to other locations in one or more of the memory units. For example, it may be desirable to remove one of the memory units when the memory unit is performing unreliably. To prevent the loss of data that may be stored in the memory unit to be removed, the computer system employing the memory unit is often shut down before removing the memory unit. Once the memory unit has been removed, the computer system is rebooted. The shutting down and rebooting of the computer system is an obviously undesirable consequence of removing the memory unit, since the computer system is unable to run any applications until the reboot is completed.
Some techniques have been developed that allow a memory unit to be removed from the computer system without shutting down the computer system. For example, the processor""s virtual memory mapping system may be used to re-map the physical addresses. This results in the temporary halting of applications and the copying of data from the memory unit being removed to a disk or some other data storage device until the removed memory unit is replaced by a new memory unit. The primary reason for halting the executions of applications is to prevent attempts to store to and/or retrieve from the memory unit being removed so that data errors are prevented. All threads in a multi-threaded application as well as the I/O system should always have a consistent view of a memory location.
Once the removed memory unit has been replaced, the aforementioned data copied from the removed memory unit is then written to the new memory unit. Then, execution of applications is resumed. While the foregoing techniques lessen the amount of time that the computer system is unable to run applications, there is still a finite amount of time in which the computer system is unable to run an application.
It should be noted that there are other situations in which it may be desirable to move data. For example, another situation in which moving data in memory may be desirable is to improve the interleave for a memory range and, therefore, improve system performance. Whenever data is moved from and/or to a different memory unit, it is desirable to minimize the amount of time that the computer system is unable to run an application.
Thus, a heretofore unaddressed need exists in the industry for providing a system and method for dynamically reallocating memory in a computer system such that data is moved among different memory locations without requiring the computer system to halt execution of applications.
The present invention overcomes the inadequacies and deficiencies of the prior art as discussed hereinbefore. Generally, the present invention provides a system and method for dynamically reallocating computer memory.
In architecture, the system of the present invention utilizes a plurality of memory units, a mapper, and a system manager. Each of the memory units includes memory locations for storing data. These data values are accessed in response to requests transmitted from one or more processing units coupled to the mapper. When the mapper receives a request to access a data value, the mapper translates a bus address included in the request into a memory unit address based on one of a plurality of mappings maintained by the mapper. The memory unit address identifies one of the memory locations that is storing the requested data value.
In moving the data value from a source memory location to a destination memory location, a pointer that identifies the source memory location is stored in the destination memory location. While the pointer is stored in the destination memory location, the system manager causes the mappings to be updated such that the mapper is configured to translate the aforementioned bus address into a memory unit address identifying the destination memory location. If the bus address of a request received by the mapper is translated into a memory unit address identifying the destination memory location before the aforementioned data value is moved from the source memory location to the destination memory location, then the pointer will be accessed in response to the request. Therefore, accessing the pointer indicates that the requested data value should be accessed from the source memory location rather than the destination memory location.
The present invention can also be viewed as providing a method for dynamically moving data from one memory location to another memory location. The method can be broadly conceptualized by the following steps: receiving requests to access data, the requests including bus addresses; mapping the bus addresses to memory unit addresses based on a plurality of mappings, the memory unit addresses identifying a plurality of memory locations including a destination memory location and a source memory location; accessing data based on the memory unit addresses mapped from the bus addresses; dynamically moving a data value from the source memory location to the destination memory location; and updating the mappings such that a bus address mapped to a memory unit address identifying the source memory location is mapped to a memory unit address identifying the destination memory location.
Other features and advantages of the present invention will become apparent to one skilled in the art upon examination of the following detailed description, when read in conjunction with the accompanying drawings. It is intended that all such features and advantages be included herein within the scope of the present invention and protected by the claims.